SoPC-based DMA for PCI Express DAQ cards
Abstract
Express (PCIe) direct memory access (DMA) interface for
implementation on Intel Cyclone V FPGAs. The DMA engine was
designed to support DAQ tasks including continuous pretriggering
acquisition for transient analysis and multichannel
transmission. Proposed solution is based on Intel SoPC resources.
Performance of the interface has been evaluated on Terasic OVSK
board (PCIe Gen2 x4). Target configuration of this interface is
based on the Avalon-MM Hard IP for Cyclone V PCIe core and
Jungo WinDriver x64 for Windows. A sample speed of 1200 MB/s
has been reported for DMA writes to PCIe memory.
Full Text:
PDFReferences
PCI Express Base Specification, rev. 3.0, PCI-SIG, Nov. 2010
A. Wójcik, R. Łukaszewski, R. Kowalik, W. Winiecki, “Nonintrusive Appliance Load Monitoring: An Overview, Laboratory Test Results and Research Directions”, Sensors, 2019, 19, 3621
A. Wójcik, P. Bilski, R. Łukaszewski, K. Dowalla, R. Kowalik, “Identification of the State of Electrical Appliances with the Use of a Pulse Signal Generator”, Energies, 2021, 14, 673.
K. N. Trung, E. Dekneuvel, B. Nicolle, O. Zammit, C. N. Van, G. Jacquemod, “Using FPGA for Real Time Power Monitoring in a NIALM System”, In Proc. 2013 IEEE International Symposium on Industrial Electronics (ISIE), 2013, pp. 1-6
Intel Corporation, Modular Scatter-Gather DMA Core, In Embedded Peripherals IP User Guide v. 18.1
Intel Corporation, Intel® Quartus® Prime Standard Edition User Guide v. 18.1, Platform Designer
Intel Corporation, Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe Solutions User Guide, UG-01110, 2020
Intel Corporation,V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide, UG-01154, 2016
WinDriver, https://www.jungo.com/st/products/windriver/wd_windows/
OpenVINO Stater Kit GT Edition User Manual, available on https://www.terasic.com.tw/
L. Rota, M. Caselle, S. Chilingaryan, A. Kopmann, M. Weber, “A PCIe DMA Architecture for Multi-Gigabyte Per Second Data Transmission”, IEEE Transactions on Nuclear Science, vol. 62, no. 3, 2015, pp. 972 - 976
A. Byszuk, J. Kołodziejski, G. Kasprowicz, K. Późniak, W. M. Zabołotny “Implementation of PCI Express bus communication for FPGA-based data acquisition systems”, In Proceedings of SPIE Vol. 8454, 2015
L. Boyang, “Research and Implementation of XDMA High Speed Data Transmission IP Cored Based on PCI Express and FPGA”, in 2019 IEEE 1st International Conference on Civil Aviation Safety
Refbacks
- There are currently no refbacks.
International Journal of Electronics and Telecommunications
is a periodical of Electronics and Telecommunications Committee
of Polish Academy of Sciences
eISSN: 2300-1933