Design of low–power 4-bit Flash ADC using Multiplexer based encoder in 90nm CMOS process
Abstract
This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence open-loop comparator and mux-based encoder are used to obtain improved performance. Simulation results shows that the simulated design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz and supply voltage of 1V.
Full Text:
PDFReferences
Abdullah S. Almansouri, Abdullah Alturki, Hossein Fariborzi, Khaled N. Salama and Talal Al-Attar “A 12.4fJ-FoM 4-bit flash ADC based on the strong ARM architecture.” IEEE 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME),2018, 10.1109/PRIME.2018.8430349
Mostafa M. Ayesh, Sameh Ibrahim, Mohamed M. Aboudina “A 15.5-mW 20-GSps 4-bit charge-steering flash ADC”, IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS),2015, 10.1109/MWSCAS.2015.7282153.
Shylu D.S.,Jackuline Moni D.,Nivetha G.(2016) “Design and Power Optimization of High-Speed Pipelined ADC with Programmable Gain Amplifier for Wireless Receiver Applications”, Wireless Personal Communication, Springer,90,657-678, 10.1007/s11277-016-3186-z
Shylu D.S., Jackuline Moni D., (2016),“Design of low power dynamic comparator with reduced kick back noise using clocked PMOS technique”, Journal of Electrical Engineering (JEE), 16(3),1-10.
Shylu D.S.,Jackuline Moni D. (2014) “A 1.8V 22mW 10 bit 165 MSPS Pipelined ADC for Video Applications”, WSEAS Transactions on Circuits and systems,13, 343-355.
Shahriar Shahramian Sorin P. Voinigescu, Anthony Chan Carusone.. “A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees” IEEE Journal of Solid-State Circuits ,44(6) , 2009, 1709 – 1720, 710.1109/JSSC.2009.2020657
Khaled Ali Shehata, Hanady Husien, Hani Fekri Ragai “ A 1.5 GSPS 4-bit flash ADC using 0.18um CMOS”, Microelectronics, 2007, 10.1109/ICM.2007.4497718.
Ying-Zu Lin, Yu-Chang Lieu and Soon-Jyh Chang “A 0.35-1v 0.23 GS/s 4-bit low power flash ADC for a solar powered wireless module.” Proceedings of International Symposium on VLSI Design, Automation and Test, DOI: 10.1109/VDAT.2010.5496748.
Dong-Ryeol Oh, Jong-In Kim, Min-Jae Seo, Jin Gwang Kim, Seung-Tak Ryu “A 6-bit 10- GS/s 63-mW 4x t1 time-domain interpolating flash ADC in 65nm CMOS” ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) 10.1109/ESSCIRC.2015.7313892.
Mehdi Nasrollahpour, “Extra bit generation for high speed time based flash ADCs in 65nm CMOS”, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), DOI: 10.1109/ISCAS.2018.8351432.
Hairong Yu and Mau-Chang Frank Chang. “A 1-v 1.25-GS/s 8-bit self calibrated flash ADC in 90 nm digital CMOS” IEEE Transactions on Circuits and Systems II: Express Briefs,55(7) ,2008),668-672, DOI: 10.1109/TCSII.2008.921596.
Robert Loehr, Markus Kempf, Frank Ohnhaeuser,Juergen Roeber, Robert Weigel, Andreas Baenisch “Implementation of a high speed flash ADC for high performance pipeline ADCs in 180 nm CMOS process, 2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), DOI: 10.1109/ISPACS.2015.7432788
G.L.Madhumati, Mr.K.Ramakoteswara Rao, Dr.M.Madhavilatha “Comparison of 5-bit thermometer to binary decoders in 1.8v, 0.18um CMOS technology for flash ADCs”,2015, Tehnicki Vjesnik 22(6):1425-1431, DOI:
17559/TV-20130914070012.
Titu Mary Ignatius, Jobin.K.Antony, Shilpa Rose Mary. “Implementation of high performance dynamic flash ADC” 2014 Annual International Conference on Emerging Research Areas: Magnetics, Machines and Drives (AICERA/iCMMD),
DOI: 10.1109/AICERA.2014.6908268.
.
K.N. Hosur, Darpiyappa, Shivanand, Vijay, Nagesha, Girish, Attimard, Harish, Kittur “Design of 4-bit flash ADC using TMCC and NOR ROM encoder in 90nm CMOS technology”, 2015 International Conference on Trends in Automation, Communications and Computing Technology (I-TACT-15), DOI: 10.1109/ITACT.2015.7492673.
D.S.Shylu Sam,J.Arolin,D.Jackuline Moni (2018) “ Design of 12 Bit 100MS/s Low Power Delta Sigma ADC Using Telescopic Amplifier, International Conference on Circuits,Devices and Systems (ICDCS’18),263-265, DOI: 10.1109/ICDCSyst.2018.8605152
D.S.Shylu,S.Jasmine,D.Jackuline Moni(2018)” A Low Power Dynamic Comparator for a 12-bit Pipelined Successive Approximation Register (SAR) ADC” International Conference on Circuits,Devices and Systems (ICDCS’18),339-342, DOI: 10.1109/ICDCSyst.2018.8605130.
Refbacks
- There are currently no refbacks.
International Journal of Electronics and Telecommunications
is a periodical of Electronics and Telecommunications Committee
of Polish Academy of Sciences
eISSN: 2300-1933
