High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic

Authors

  • Reza Faghih Mirzaee Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran http://orcid.org/0000-0001-7175-0229
  • Akram Reza Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran

Abstract

This paper presents a ternary (4:2) compressor, which is an important component in multiplication. However, the structure differs from the binary counterpart since the ternary model does not require carry signals. The method of capacitive threshold logic (CTL) is used to achieve the output signals directly. Unlike the previously presented similar structure, the entire capacitor network is divided into two parts. This segregation results in higher reliability and robustness against unwanted process, voltage, and temperature (PVT) variations. Simulations are performed by HSPICE and 32nm CNFET technology. Simulation results demonstrate about 94% higher performance in terms of power-delay product (PDP) for the new design over the previous one.

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Published

2017-10-31

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Microelectronics, nanoelectronics