A Method to Support Diagnostics of Dynamic Faults in Networks of Interconnections

Authors

  • Tomasz Garbolino Silesian University of Technology

Abstract

The article is devoted to the method facilitating the diagnostics of dynamic faults in networks of interconnection in systems-on-chips. It shows how to reconstruct the erroneous test response sequence coming from the faulty connection based on the set of signatures obtained as a result of multiple compaction of this sequence in the MISR register with programmable feedback. The Chinese reminder theorem is used for this purpose. The article analyzes in detail the various hardware realizations of the discussed method. The testing time associated with each proposed solution was also estimated. Presented method can be used with any type of test sequence and test pattern generator. It is also easily scalable to any number of nets in the network of interconnections. Moreover, it supports finding a trade-off between area overhead and testing time.

Author Biography

Tomasz Garbolino, Silesian University of Technology

Assistant Professor at the Faculty of Automatic Control, Electronics and Computer Science

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Published

2018-07-20

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Section

VHDL, Hardware Intelligence