A NEW APPROACH OF AN ERROR DETECTING AND CORRECTING CIRCUIT BY ARITHMETIC LOGIC BLOCKS

Authors

  • kavitha P.S Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia,
  • FAZIDA HANIM HASHIM Hashim Department of Electrical, Electronic & Systems Engineering,University Kebangsaan Malaysia
  • NOORFAZILA KAMAL kamal Department of Electrical, Electronic & Systems Engineering,University Kebangsaan Malaysia

Abstract

This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area.

 

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Published

2024-04-19

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Section

Microelectronics, nanoelectronics