Low Power and Improved Speed Montgomery Multiplier using Universal Building Blocks

Authors

Abstract

This paper describes the arithmetic blocks based on Montgomery Multiplier (MM), which reduces complexity, gives lower power dissipation and higher operating frequency. The main objective in designing these arithmetic blocks is to use modified full adder structure and carry save adder structure that can be implemented in algorithm based MM circuit. The conventional full adder design acts as a benchmark for comparison, the second is the modified Boolean equation for full adder and third design is the design of full adder consisting of two XOR gate and a 2-to-1 Multiplexer. Besides Universal gates such as NOR gate and NAND gate, full adder circuits are used to further improve the speed of the circuit. The MM circuit is evaluated based on different parameters such as operating frequency, power dissipation and area of occupancy in FPGA board. The schematic designs of the arithmetic components along with the MM architecture are constructed using Quartus II tool, while the simulation is done using Model sim for verification of circuit functionality which has shown improvement on the full adder design with two XOR gate and one 2-to-1 Multiplexer implementation in terms of power dissipation, operating frequency and area.

Author Biography

Velrajkumar Pitchandi, CMR Institute of Technology, Bangalore, India.

Associate Professor,

Department of Electrical and Electronics Engineering.

References

Thomas Blum “Montgomery Modular Exponentiation on Reconfigurable Hardware” ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic, IEEE Computer Society Washington, DC, USA , 1999, pp-70-78.

Quartus® II Introduction for VHDL Users, ALTERA® CORPORATION APRIL 2011.

Amanor, David & Paar, C & Pelzl, Jan & Bunimov, V & Schimmler, Manfred. (2005). Efficient hardware architectures for modular multiplication on FPGAs. 2005. 539 - 542. 10.1109/FPL.2005.1515780.

Tang, Guang-Ming & Takagi, Kazuyoshi & Takagi, Naofumi. (2017). 32×32-bit 4-bit Bit-Slice Integer Multiplier for RSFQ Microprocessors. IEEE Transactions on Applied Superconductivity. PP. 1-1. 10.1109/TASC.2017.2662700.

Shinde, Kunjan D., Nidagundi, Jayashree C. (2014).Design of fast and efficient 1-bit full adder and its performance analysis, 2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), pp- 1275 – 1279.

Asirbad Behera, Manas Ranjan Jena, Abhinna Das, Narendra Kumar Pattnayak, (2014),“Design of an Efficient Dedicated Low Power High Speed Full Adder”, Journal of Embedded Systems, Archive, Vol. 2 , issue 3 2014, pp.35-28.

Manoj Kumar , Sandeep K. Arya and Sujata Pandey (2011), “Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate”, International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, 2011, pp 47-59.

P. Montgomery (1985), “Modular multiplication without trial division,” Mathematics of Computation, vol. 44, pp. 519–521, 1985.

Guilherme Perin, Daniel Gomes Mesquita, and João Baptista Martins (2011), “Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation”, International Journal of Reconfigurable Computing, Volume 2011, Article ID 127147, 10 pages.

C. Senthilpari, K. Diwakar and A.K. Singh, “Low power, low latency, high throughput 16 bit CSA adder using Non Clocked Pass-transistor logic”, Journal of Circuits, Systems and Computers, May 2009, Vol. 18, No. 03: pp. 581-596.

C Senthilpari, G Ramanamurthy, P Velrajkumar, An efficient EPI and energy consumption of 32 bit ALU using Shannon theorem based adder approach, WSEAS Transactions on Circuits and Systems 10 (7), pp-231-238.

Akbar Bermana (2012)“ A new simulation of a 16-bit Ripple Carry Adder and a 1-bit Skip Carry Adder” International journal of scientific &Technology Research Vol.1 Issue 2, 2012, pp-78-84.

Raminder Preet Pal Singh, Parveen Kumar , Blwinder Singh (2009), “Performance Analysis of 32-Bit Array Multiplier with a Carry Save Adder and with a Carry-Look-Ahead Adder”, International Journal of Recent Trends in Engineering, Vol 2, No. 6, 2009, pp 83-86.

Padma Devi, Ashima Girdher, Balwinder Singh, “Improved Carry Select Adder with Reduced Area and Low Power Consumption”, International Journal of Computer Applications (0975 – 8887) Volume 3 – No.4, 2010, pp 14-18.

C Senthilpari A Low-power and High-performance Radix-4 Multiplier Design Using a Modified Pass-transistor Logic Technique, IETE Journal of Research 57 (2), pp 149-155.

Downloads

Published

2024-04-19

Issue

Section

Signals, Circuits, Systems