An Efficient Two-phase Clocked Sequential Multiply -Accumulator unit for Image blurring

Authors

  • Rashmi Samanth Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal-576 104
  • Subramanya G. Nayak Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal-576 104. http://orcid.org/0000-0001-7720-4392

Abstract

The multiply-accumulator (MAC) unit is the basic integral computational block in every digital image and digital signal processor. As the demand grows, it is essential to design these units in an efficient manner to build a successful processor. By considering this into account, a power-efficient, high-speed MAC unit is presented in this paper. The proposed MAC unit is a combination of a two-phase clocked modified sequential multiplier and a carry-save adder (CSA) followed by an accumulator register. A novel two-phase clocked modified sequential multiplier is introduced in the multiplication stage to reduce the power and computation time. For image blurring, these multiplier and adder blocks are subsequently incorporated into the MAC unit. The experimental results demonstrated that the proposed design reduced the power consumption by 52% and improved the computation time by 4% than the conventional architectures. The developed MAC unit is implemented using 180nm standard CMOS technology using CADENCE RTL compiler, synthesized using XILINX ISE and the image blurring effect is analyzed using MATLAB.

Author Biographies

Rashmi Samanth, Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal-576 104

Presently working as Research scholar in the Department of Electronics & Communication Engineering, Manipal Institute of Technology, Manipal. She received her B.E degree in Electronics & Communication Engineering and the M.Tech degree in Microelectronics from Manipal Institute of Technology, Manipal. Her research interests are in fields of electronics, digital systems, processor architecture and VLSI.

 

Subramanya G. Nayak, Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal-576 104.

Presently working as Professor and Head in the Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal. Dr. Nayak has B.E degree in E and C Engineering, M. Tech in Biomedical Engineering and Ph.D., in Electrical and Electronics Engineering with specialization in Pattern Recognition. His research areas of interest are in the field of Processor Architecture design and applications.

References

M. Masadeh, O. Hasan and S. Tahar, “Input-conscious approximate multiply-accumulate (mac) unit for energy-efficiency,” IEEE Access, 7, pp.147129-147142. DOI:10.1109/ACCESS.2019.2946513

M.C. Shin, S.H. Kang, and I.C Park, “An area-efficient iterative modified-booth multiplier based on self-timed clocking,” In Proc. IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001 Sep 23: IEEE. pp. 511-512. DOI:10.1109/ICCD.2001.955079

W.C. Yeh and C.W Jen, “High-speed Booth encoded parallel multiplier design,” IEEE transactions on computers, 49(7):692-701, 2000. DOI:10.1109/12.863039

N. Kaur and R.K Patial, “Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA,” International Journal of Computer Applications. 975:8887, 2013.

S. Shrivastva and Pankaj Gulhane, “Comparative Analysis on Power and Delay Optimization of Various Multipliers using VHDL,” International Journal of Electrical and Electronics Research, 2014 2(3):182-91.

N. Honarmand, M.R. Javaheri, N. Sedaghati-Mokhtari and A. Afzali-Kusha, “Power efficient sequential multiplication using pre-computation,” In 2006 IEEE International Symposium on Circuits and Systems. pp. 4. DOI:10.1109/ISCAS.2006.1693183

K. Babulu and G. Parasuram, “FPGA Realization of Radix-4 Booth Multiplication Algorithm for High-Speed Arithmetic Logics,” International Journal of Computer Science and Information Technologies. 2(5), 2102-7, 2011.

R. Das, G. K Singh and R.M. Mehra. “Two-phase clocking scheme for low-power and high-speed VLSI,” Int. J. Adv. Eng. Sci. Technol, 2(2):225-30, 2013.

N. A. Nayan, Y. Takahashi and T. Sekine, “LSI implementation of a low-power 4× 4-bit array two-phase clocked adiabatic static CMOS logic multiplier,” Microelectronics Journal, 43(4):244-9,2012. DOI:10.1016/j.mejo.2011.12.013

K. Kajstura and D. Kania, “Low power synthesis of finite state machines-state assignment decomposition algorithm,” Journal of Circuits, Systems and Computers,27(03):1850041, Mar 7, 2018. DOI:10.1142/S021812661850041X

F. Carbognani, F. Bürgin, N. Felber, H. Kaeslin and W. Fichtner, “Two-phase clocking and a new latch design for low-power portable applications,” In International Workshop on Power and Timing Modeling, Optimization and Simulation. Springer, Berlin, Heidelberg. 2005 Sep 20, pp. 446-455.

K. Kato, Y. Takahashi, and T. Sekine, “Two phase clocking subthreshold adiabatic logic,” In 2014 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE 2014 Jun 1 pp. 598-601. DOI:10.1109/ISCAS.2014.6865206

S. Erniyazov and J.C Jeon, “Carry save adder and carry look ahead adder using inverter chain based coplanar QCA full adder for low energy dissipation,” Microelectronic Engineering. 211:37-43, Apr 15, 2019. 10.1016/j.mee.2019.03.015

Y. Zhang Y, L. Okamura, and T. Yoshihara, “An energy efficiency 4-bit multiplier with two-phase non-overlap clock driven charge recovery logic,” IEICE transactions on electronics, 94(4):605-12, Apr 1, 2011.

DOI:10.1587/transele.E94.C.605

K.C. Kuo and Chou CW, “Low power and high-speed multiplier design with row bypassing and parallel architecture,”. Microelectronics Journal,41(10):639-50, Oct 1, 2010. DOI: 10.1142/S021812661750030X

M.S. Kumar, D.A Kumar and P. Samundiswary, “Design and performance analysis of Multiply-Accumulate (MAC) unit” In International Conference on Circuits, Power and Computing Technologies [ICCPCT-2014], 2014 Mar 20 (pp. 1084-1089). IEEE. 10.1109/ICCPCT.2014.7054782

M. Madheswaran and S. Saravanan, “Design and Analysis of Low Power Multiply and Accumulate Unit Using Pixel Properties Reusability Technique for Image Processing Systems,” ICTACT Journal on Image and Video Processing, 459-66, Aug. 2012. DOI: 10.21917/ijivp.2012.0065

P.I. Khan and R.S. Mishra, “Comparative analysis of different algorithm for design of high-speed multiplier accumulator unit (MAC),” Indian Journal of science and technology, 9(8), Feb. 2016. DOI: 10.17485/ijst/2016/v9i8/83614

K. Singh and D. Kumar, “Modified booth multiplier with carry select adder using 3-stage pipelining technique,” International Journal of Computer Applications, 44(14):35-8, Apr. 2012. DOI:10.5120/6334-8710

Y.N Rao, G.S. Raju, P. Raja, “Design and performance evaluation of high-speed MAC unit with parallel pipeline technology,” International Journal of Computer Applications,1;106(4), Jan. 2014. DOI: 10.5120/18506-9575

Downloads

Published

2024-04-19

Issue

Vol. 68 No. 2 (2022)

Section

Signals, Circuits, Systems

License

Copyright (c) 2022 International Journal of Electronics and Telecommunications

Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.

1. License

The non-commercial use of the article will be governed by the Creative Commons Attribution license as currently displayed on https://creativecommons.org/licenses/by/4.0/.

2. Author’s Warranties

The author warrants that the article is original, written by stated author/s, has not been published before, contains no unlawful statements, does not infringe the rights of others, is subject to copyright that is vested exclusively in the author and free of any third party rights, and that any necessary written permissions to quote from other sources have been obtained by the author/s. The undersigned also warrants that the manuscript (or its essential substance) has not been published other than as an abstract or doctorate thesis and has not been submitted for consideration elsewhere, for print, electronic or digital publication.

3. User Rights

Under the Creative Commons Attribution license, the author(s) and users are free to share (copy, distribute and transmit the contribution) under the following conditions: 1. they must attribute the contribution in the manner specified by the author or licensor, 2. they may alter, transform, or build upon this work, 3. they may use this contribution for commercial purposes.

4. Rights of Authors

Authors retain the following rights:

- copyright, and other proprietary rights relating to the article, such as patent rights,

- the right to use the substance of the article in own future works, including lectures and books,

- the right to reproduce the article for own purposes, provided the copies are not offered for sale,

- the right to self-archive the article

- the right to supervision over the integrity of the content of the work and its fair use.

5. Co-Authorship

If the article was prepared jointly with other authors, the signatory of this form warrants that he/she has been authorized by all co-authors to sign this agreement on their behalf, and agrees to inform his/her co-authors of the terms of this agreement.

6. Termination

This agreement can be terminated by the author or the Journal Owner upon two months’ notice where the other party has materially breached this agreement and failed to remedy such breach within a month of being given the terminating party’s notice requesting such breach to be remedied. No breach or violation of this agreement will cause this agreement or any license granted in it to terminate automatically or affect the definition of the Journal Owner. The author and the Journal Owner may agree to terminate this agreement at any time. This agreement or any license granted in it cannot be terminated otherwise than in accordance with this section 6. This License shall remain in effect throughout the term of copyright in the Work and may not be revoked without the express written consent of both parties.

7. Royalties

This agreement entitles the author to no royalties or other fees. To such extent as legally permissible, the author waives his or her right to collect royalties relative to the article in respect of any use of the article by the Journal Owner or its sublicensee.

8. Miscellaneous

The Journal Owner will publish the article (or have it published) in the Journal if the article’s editorial process is successfully completed and the Journal Owner or its sublicensee has become obligated to have the article published. Where such obligation depends on the payment of a fee, it shall not be deemed to exist until such time as that fee is paid. The Journal Owner may conform the article to a style of punctuation, spelling, capitalization and usage that it deems appropriate. The Journal Owner will be allowed to sublicense the rights that are licensed to it under this agreement. This agreement will be governed by the laws of Poland.

By signing this License, Author(s) warrant(s) that they have the full power to enter into this agreement. This License shall remain in effect throughout the term of copyright in the Work and may not be revoked without the express written consent of both parties.