New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

Authors

  • Tomasz Garbolino Silesian University of Technology

Abstract

The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built-in blocks within a System on a Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitance nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence.

Author Biography

Tomasz Garbolino, Silesian University of Technology

Assistant Professor at the Faculty of Automatic Control, Electronics and Computer Science, Silesian University of Technology, Gliwice, Poland

References

N. Ahmed, M. H. Tehranipour, M. Nourani, “Extending JTAG for testing signal integrity in SoCs”, in Proc. Design, Automation and Test in Europe – DATE’03, Munich, Germany, 2003, pp. 218-223.

Aniket, R. Arunachalam, “A novel algorithm for testing crosstalk induced delay faults in VLSI circuits”, in Proc. 18th Int. Conf. on VLSI Design, Kolkata, India, 2005, pp. 479-484.

X. Aragones, J. L. González, F. Moll, and A. Rubio, “Noise Generation and Coupling Mechanisms in Deep-Submicron ICs”, IEEE Design & Test Computers, vol.19, no.5, pp. 27-35, September October 2002.

A. Attarha, M. Nourani, “Testing interconnects for noise and skew in gigahertz SoCs”, in Procs. of IEEE Int. Test Conf. – ITC’01, Baltimore, MD, USA, 2001, pp. 305-314.

L. Benini, G. De Micheli, “Networks on Chips: A New SoC Paradigm”, Computer, vol. 35 no. 1, pp. 70 78, January 2002.

M. Botelho, F. L. Kastensmidt, M. Lubaszewski, E. Cota, L. Carro, „A Broad Strategy to Detect Crosstalk Faults in Network-on-Chip Interconnects”, in Proc. 2010 18th IEEE/IFIP Int. Conf. on VLSI and System-on-Chip, Madrid, Spain, 2010, pp. 298-303.

M. Cuviello, S. Dey, Xiaoliang Bai, Yi Zhao, “Fault modeling and simulation for crosstalk in system-on-chip interconnects”, in Proc. 1999 IEEE/ACM Int. Conf. on Computer-Aided Design, San Jose, CA, USA, 1999, pp. 297-303.

W. J. Dally, B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks”, in Procs. 38th IEEE/ACM Design Automation Conference – DAC’01, Las Vegas, NV, USA, 2001, pp. 683-689.

T. Garbolino, “Designing of test pattern generators for stimulation of crosstalk faults in bus-type connections.”, Proc. 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems – DDECS’2014, Warsaw, Poland, April 23-25, 2014, pp. 270-273.

C. Grecu, P. P. Pande, A. Ivanov, R. Saleh, "Structured Interconnect Architecture: A Solution for the Non-Scalability of Bus-Based SoCs”, in Proc. Great Lakes Symposium on VLSI – GLSVLSI’04, New York, NY, USA, 2004, pp 192-195.

C. Grecu, P. Pande, A. Ivanov, R. Saleh, “BIST for Network-on-Chip Interconnect Infrastructures”, in Proc. 24th IEEE VLSI Test Symposium – VTS'06, Berkeley, CA, USA, 2006, pp. 30-35.

P. Guerrier, A. Greiner, ”A Generic Architecture for on chip Packet switched Interconnections”, Proc. Design, Automation & Test in Europe – DATE’00, Paris, France, 2000, pp. 250-256.

G. Haiyun, “Survey of Dynamically Reconfigurable Network on Chip”, in Proc. 2011 Int. Conf. on Future Computer Sciences and Application - ICFCSA 2011, Hong Kong, China, 2011, pp. 200-203.

A. Jutman, “At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults”, in Procs. 9th IEEE European Test Symposium – ETS’04, Ajaccio, France, 2004, pp. 2-7.

M. Kopeć, T. Garbolino, K. Gucwa, A. Hławiczka, “Test-per-clock detection, localization and identification of interconnect faults”, in Procs. 11th IEEE European Test Symposium – ETS’06, Southampton, United Kingdom, 2006, pp. 233-238.

M. Kopeć, T. Garbolino, K. Gucwa, A. Hławiczka, “On application of polynomial algebra for identification of dynamic faults in interconnects”, Electronics and Telecommunications Quarterly, vol. 54, no. 1, pp. 29-41, 2008.

S. Kumar, et al., “A Network on Chip Architecture and Design Methodology,” in Procs. IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, USA, 2002, pp. 117-124.

K. Shu-Min Li; Chung Len Lee; Chauchin Su; J.E. Chen, “A unified approach to detecting crosstalk faults of interconnects in deep sub micron VLSI”, in Procs. 13th IEEE Asian Test Symposium, Kenting, Taiwan, 2004, pp. 145-150.

K.S.-M. Li, Yi-Yu Liao, Yuo-Wen Liu, Jr-Yang Huang, “IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency”, in Procs. 18th IEEE Asian Test Symposium – ATS 2009, 2009, Taichung, Taiwan, pp. 269-274.

P. Magarshack, P.G. Paulin, “System-on-Chip beyond the Nanometer Wall”, in Procs. 40th IEEE/ACM Design Automation Conference – DAC’03, Anaheim, USA, 2003, pp. 419-424.

P. Nordholz, D. Treytnar, J. Otterstedt, H. Grabinski, D. Niggemeyer, T.W. Williams, “Signal Integrity Problems in Deep Submicron arising from Interconnects between Cores”, in Procs. IEEE VU1 Test Symposium, 1998, pp. 28-33.

M. Nourani, A. Attarha, “Built-In Self-Test for Signal Integrity”, in Proc. 38th IEEE Design Automation Conference – DAC 2001, Las Vegas, NV, USA, 2001, pp. 792-797.

R. Nourmandi-Pour, A. Khadem-Zadeh, A. M. Rahmani, “An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip”, Elsevier Journal of Microelectronics, vol. 41, no. 7, pp. 417 429, July 2010.

R. Nourmandi-Pour, N. Mousavian, “A fully parallel BIST based method to test the crosstalk defects on the inter-switch links in NOC”, Microelectronics Journal, vol. 44, no. 3, pp. 248-257, March 2013.

P. Pande, C. Grecu, A. Ivanov, R. Saleh, G. De Micheli, “Design, synthesis, and test of networks on chips”, IEEE Design & Test of Computers, vol. 22, no. 5, pp. 404-413, 2005.

R. Pendurkar, A. Chatterjee, Y. Zorian, “Switching Activity Generation with Automated BIST Synthesis for Performance Testing of Interconnects”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp. 1143-1158, 2001.

Y.-L. Peng, C.-W. Wu, J.-J. Liou, C.-T. Huang, “BIST-based diagnosis scheme for field programmable gate array interconnect delay faults”, IET Computers & Digital Techniques, vol. 1, no. 6, pp. 716-723, November 2007.

T. Rudnicki, T. Garbolino, K. Gucwa, A. Hławiczka, “Effective BIST for crosstalk faults in interconnects”, in Proc. 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS'2009, Liberec, Czech Republic, 2009, pp. 164-169.

K. Sekar, S. Dey, “LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects”, in Journal of Electronic Testing: Theory and Applications, vol. 19, no. 6, pp. 113-123, 2003.

A. Sinha, S. K. Gupta, M. A. Breuer, “Validation and test issues related to noise induced by parasitic inductances of VLSI interconnects”, IEEE Transactions on Advanced Packaging, vol. 25, no. 3, pp. 329–339, August 2002.

Sunghoon Chun, Yongjoon Kim and Sungho Kang, “MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs”, Journal of Electronic Testing: Theory and Applications, vol. 23, no. 4, pp. 357-362, August 2007.

C. Su, W. Tseng, “Configuration free SoC interconnect BIST methodology”, in Procs. IEEE International Test Conference, “Tackling Test Tradeoffs”, Baltimore, MD, USA, 2001, pp. 1033-1038.

O. Tayan, “Networks-on-Chip: Challenges, trends and mechanisms for enhancements”, in Proc. The 3rd International Conference on Information and Communication Technologies – ICICT’09, Karachi, Pakistan, 2009, pp. 57-62.

M. H. Tehranipour, N. Ahmed, M. Nourani, “Multiple transition model and enhanced boundary scan architecture to test interconnects for signal integrity”, in Proc. 21st Int. Conf. on Computer Design, San Jose, CA, USA, 2003, pp. 554-559.

M. H. Tehranipour, N. Ahmed, M. Nourani, “Testing SoC interconnects for signal integrity using extended JTAG architecture”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 23, no. 5, pp. 800-811, May 2004.

C. Tsai, J. Wu, C. Kao, T. Lee, R. Hsiao, “Coupling-aware RLC based clock routing for crosstalk minimization”, in Proc. 2006 IEEE International Symposium on Circuits and Systems – ISCAS’06, Island of Kos, Greece, 2006, pp. 497-500.

Xiaoliang Bai, S. Dey, J. Rajski, “Self-Test Methodology for At Speed Test of Crosstalk in Chip Interconnects, in Proc. 2000 37th IEEE Design Automation Conference – DAC’00, Los Angeles, CA, USA, 2000, pp. 619-624.

H. Zhou, D. F. Wang, “Global routing with crosstalk constraints”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 18, no. 11, pp. 1683-1688, November 1999.

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Published

2015-03-16

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Section

Analog Electronics