The Impact of Noise and Mismatch on SAR ADCs and a Calibratable Capacitance Array Based Approach for High Resolutions

Authors

  • Jan Henning Mueller Integrated Analog Circuits and RF Systems Laboratory, RWTH Aachen University, Aachen
  • Sebastian Strache Integrated Analog Circuits and RF Systems Laboratory, RWTH Aachen University, Aachen
  • Laurens Busch Integrated Analog Circuits and RF Systems Laboratory, RWTH Aachen University, Aachen
  • Ralf Wunderlich Integrated Analog Circuits and RF Systems Laboratory, RWTH Aachen University, Aachen
  • Stefan Heinen Integrated Analog Circuits and RF Systems Laboratory, RWTH Aachen University, Aachen

Abstract

This paper describes widely used capacitor structures for charge-redistribution (CR) successive approximation register (SAR) based analog-to-digital converters (ADCs) and analyzes their linearity limitations due to kT/C noise, mismatch and parasitics. Results of mathematical considerations and statistical simulations are presented which show that most widespread dimensioning rules are overcritical. For high-resolution CR SAR ADCs in current CMOS technologies, matching of the capacitors, influenced by local mismatch and parasitics, is a limiting factor. For high-resolution medium-speed CR SAR ADCs, a novel capacitance array based approach using in-field calibration is proposed. This architecture promises a high resolution with small unit capacitances and without expensive factory calibration as laser trimming.

References

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Published

2015-03-11

Issue

Vol. 59 No. 2 (2013)

Section

ARCHIVES / BACK ISSUES

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